Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

On 8/6/20 11:41 AM, Lu, Brent wrote:

...

I don't get this. If the platform driver already stated 240 and 960 samples why would 432 be chosen? Doesn't this mean the constraint is not applied?

Hi Pierre,

Sorry for late reply. I used following constraints in V3 patch so any period which aligns 1ms would be accepted.

• /*

• * Make sure the period to be multiple of 1ms to align the
  

• * design of firmware. Apply same rule to buffer size to make
  

• * sure alsa could always find a value for period size
  

• * regardless the buffer size given by user space.
  

• */
  

• snd_pcm_hw_constraint_step(substream->runtime, 0,

• 	   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 48);
  

• snd_pcm_hw_constraint_step(substream->runtime, 0,

• 	   SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 48);
  

432 samples is 9ms, I don't have a clue why/how CRAS might ask for this value.

It'd be a bit odd to add constraints just for the purpose of letting userspace select a sensible value.