On 15.12.2023 13:20, Mahapatra, Amit Kumar wrote:
Hello Tudor,
Hi!
-----Original Message----- From: Tudor Ambarus tudor.ambarus@linaro.org Sent: Friday, December 15, 2023 4:03 PM To: Mahapatra, Amit Kumar amit.kumar-mahapatra@amd.com; broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; michael@walle.cc; linux-mtd@lists.infradead.org; nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com; claudiu.beznea@tuxon.dev; Simek, Michal michal.simek@amd.com; linux-arm-kernel@lists.infradead.org; alsa- devel@alsa-project.org; patches@opensource.cirrus.com; linux- sound@vger.kernel.org; git (AMD-Xilinx) git@amd.com; amitrkcian2002@gmail.com Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor
On 12/15/23 10:02, Mahapatra, Amit Kumar wrote:
Hello Tudor,
Hi,
-----Original Message----- From: Tudor Ambarus tudor.ambarus@linaro.org Sent: Friday, December 15, 2023 1:40 PM To: Mahapatra, Amit Kumar amit.kumar-mahapatra@amd.com; broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; michael@walle.cc; linux-mtd@lists.infradead.org; nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com; claudiu.beznea@tuxon.dev; Simek, Michal michal.simek@amd.com; linux- arm-kernel@lists.infradead.org; alsa-devel@alsa-project.org; patches@opensource.cirrus.com; linux-sound@vger.kernel.org; git (AMD- Xilinx) git@amd.com; amitrkcian2002@gmail.com Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor
On 15.12.2023 09:55, Mahapatra, Amit Kumar wrote:
Thanks! Can you share with us what flashes you used for testing in the stacked and parallel configurations?
I used SPI-NOR QSPI flashes for testing stacked and parallel.
I got that, I wanted the flash name or device ID.
N25Q00A, MX66U2G45G, IS25LP01G & W25H02JV are some of the QSPI
flashes
on which we tested. Additionally, we conducted tests on over 30 different QSPI flashes from four distinct vendors (Miron, Winbond,
Macronix, and ISSI).
Great.
What I'm interested is if each flash is in its own package. Are they?
I'm sorry, but I don't quite understand what you mean by "if each flash in its own package."
There are flashes that are stacked at the physical level. It's a single flash with multiple dies, that are all under a single physical package.
Got it. The W25H02JV QSPI flash I mentioned earlier is a device with with four dies that are stacked at the physical level.
As I understand, your stacked flash model is at logical level. You have 2 flashes each in its own package. 2 different entities. Is my understanding correct?
Yes, that’s correct.
I'd like to contribute to your earlier point regarding the placement of the stacked layer. As you correctly highlighted, it should be in the spi-mem generic layer. For instance, when a read/write operation extends across multiple flashes (whether SPI-NOR or SPI-NAND), the stacked layer must handle the flash crossover. This requires setting the appropriate CS index in mem->spi->cs_index_mask to select the correct slave device and updating the data buffer, address & data length in spi_mem_op struct variable. Does this align with your understanding?
This was the initial idea, yes, but we'll have to see how mtd concat fits in. Maybe the abstraction can be made at the mtd level, which I suspect mtd concat does. I have to read that driver, never opened it.
Something else to consider: I see that Micron has a twin quad mode: https://media-www.micron.com/-/media/client/global/documents/products/data-s...
The micron's "Separate Chip-Select and Clock Signals" resembles the AMD's dual parallel 8-bit. Micron's "Shared Chip-Select and Clock Signals" differs from the AMD's stacked mode, as Micron uses DQ[3:0] and DQ[7:4], whereas AMD considers both as DQ[3:0].
I had a short chat with Michael and he highlighted that instead of the parallel mode, one would be better of with an octal device. I wonder whether the quad parallel is worth the effort. I see AMD can select either quad (single/stacked/parallel) or octal (single/stacked). Is the parallel mode considered obsolete for new IPs?
Cheers, ta