30 Jul
2018
30 Jul
'18
12:18 p.m.
On Mon, Jul 30, 2018 at 10:31:16AM +0100, Jon Hunter wrote:
It can be quite common for the fsync-width for DSP modes to be a single clock and so I am not sure that is makes sense to set this here always to the slot width. It maybe worth considering add a DT property for specifying the fsync width.
DSP modes only care about the rising edge of the LRCLK, the pulse can be any width without causing interoperability problems.