19 Mar
2014
19 Mar
'14
9:24 p.m.
On 03/17/2014 11:08 PM, Dylan Reid wrote:
When using an rbtree cache, there can be allocations the first time a register is accessed. This can cause an attempt to schedule while atomic in the case that the regmap is using a spinlock. This could be fixed by either initializing all the registers or using a flat cache. The register maps for tegra30_ahub and tegra30_i2s are dense and don't save much from using a tree so convert them to flat.
Tegra30 changes tested on Norrin, Tegra20 changes compile.
Tested-by: Stephen Warren swarren@nvidia.com
(On Tegra124 Venice2 and Tegra20 Seaboard/Springbank)