[alsa-devel] Understanding Atmel SSC SND_SOC_DAIFMT_CBS_CFS mode

Hi List,

I'm looking for a way to understand how to correctly configure the Atmel SSC dai on a SAMA5D3 to work in master mode with an I2S codec.

From this comment:

/* * I2S format, SSC provides BCLK and LRC clocks. * * The SSC transmit and receive clocks are generated * from the MCK divider, and the BCLK signal * is output on the SSC TK line. */

My question is: should be MCK divider configured manually? If yes how?

Actually I'm trying to poke around in atmel_ssc_dai and found a way to generate a stable bit clock, but frame clock is not working as expected.

Have you any advice on how to set correctly SSC parameters to generate a stable bit clock and frame clock?

Any advice?

Thank you!