At Mon, 20 Apr 2015 17:33:57 +0800, mengdong.lin@intel.com wrote:
From: Mengdong Lin mengdong.lin@intel.com
Only Intel Haswell and Broadwell have a separate HD-A controller (PCI device 3) for display audio, which needs to get 24MHz HD-A link BCLK from the variable display core clock through vendor specific registers EM4 & EM5. Other platforms (Baytrail, Braswell and Skylake) don't have this feature.
So this patch checks the PCI device ID of the controller in haswell_set_bclk() and only sync BCLK for HSW and BDW.
Signed-off-by: Mengdong Lin mengdong.lin@intel.com
Applied, thanks.
Takashi
diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c index 52a85d8..3052a2b 100644 --- a/sound/pci/hda/hda_i915.c +++ b/sound/pci/hda/hda_i915.c @@ -55,6 +55,12 @@ void haswell_set_bclk(struct hda_intel *hda) int cdclk_freq; unsigned int bclk_m, bclk_n; struct i915_audio_component *acomp = &hda->audio_component;
struct pci_dev *pci = hda->chip.pci;
/* Only Haswell/Broadwell need set BCLK */
if (pci->device != 0x0a0c && pci->device != 0x0c0c
&& pci->device != 0x0d0c && pci->device != 0x160c)return;if (!acomp->ops) return;
-- 1.9.1