7 Jun
2019
7 Jun
'19
1:12 p.m.
On Thu, Jun 06, 2019 at 04:01:05PM -0700, Nicolin Chen wrote:
This reverts commit 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645.
Please use subject lines matching the style for the subsystem. This makes it easier for people to identify relevant patches.
- Though ETDR and TX0~5 are not volatile but write-only registers, they should not be cached either. According to the definition of "volatile_reg", one should be put in the volatile list if it can not be cached.
There's no problem with caching write only registers, having a cache allows one to do read/modify/write cycles on them and can help with debugging. The original reason we had cache code in ASoC was for write only devices.