Hello Shengjiu,
On Thu, May 23, 2019 at 09:53:42AM +0000, S.j. Wang wrote:
/** Add fifo reset here, because the regcache_sync will* write one more data to ETDR.* Which will cause channel shift.Sounds like a bug to me...should fix it first by marking the data registers as volatile.
The ETDR is a writable register, it is not volatile. Even we change it to Volatile, I don't think we can't avoid this issue. for the regcache_sync Just to write this register, it is correct behavior.
Is that so? Quoting the comments of regcache_sync(): "* regcache_sync - Sync the register cache with the hardware. * * @map: map to configure. * * Any registers that should not be synced should be marked as * volatile."
If regcache_sync() does sync volatile registers too as you said, I don't mind having this FIFO reset WAR for now, though I think this mismatch between the comments and the actual behavior then should get people's attention.
Thank you