On Fri, Sep 02, 2016 at 12:49:51PM +0200, Sylwester Nawrocki wrote:
On 08/30/2016 04:57 PM, Sylwester Nawrocki wrote:
I will use prepare/complete as with late_suspend/early_resume power sequences are wrong as you point out. I still need to debug why there is no errors reported when the SPI controller is suspended while there are supposed to be done SPI bus transfers.
As it turns out the reason there is no any errors with late_suspend/ early_resume is that the CODEC sets its regmap's "cache only" only flag in its suspend() callback and then clears it in resume(). So any SPI transfers which might happen when SPI controller is suspended are prevented this way.
Ah of course yeah should have realised that, but yeah you still end up with the writes not actually reaching the hardware.
Thanks, Charles