23 Apr
2009
23 Apr
'09
1:15 p.m.
On Thu, Apr 23, 2009 at 12:04:05PM +0100, Alan Horstmann wrote:
Does this indicate that the implementation/drivers of i2s has a fundamental ambiguity? Is it not rigidly defined which channel should follow a rising edge of L/R clock?
It's clearly defined to be that the left channel follows the falling edge of LRCLK (ie, the left channel data is transmitted while LRCLK is low). However, not all CPUs do a wonderful job of implementing this - some of the older Samsung chips need a workaround for synchronisation, for example.