5 May
2020
5 May
'20
6:57 p.m.
- Currently Skylake does not output MCLK/FS when the back-end DAI op hw_param is called, so we cannot switch to MCLK/FS in hw_param. This patch reduces pop by letting nau8825 keep using its internal VCO clock during widget power up sequence, until SNDRV_PCM_TRIGGER_START when MCLK/FS is available. Once device resumes, the system will only enable power sequence for playback without doing hardware parameter, audio format, and PLL configure. In the mean time, the jack detecion sequence has changed PLL parameters and switched to internal clock. Thus, the playback signal distorted without correct PLL parameters. That is why we need to configure the PLL again in SNDRV_PCM_TRIGGER_RESUME case.
IIRC the FS can be controlled with the clk_ api with the Skylake driver, as done for some KBL platforms. Or is this not supported by the firmware used by this machine?
According to Ben, SKL had limitations in FW for managing the clk's back in the days. Can you point to the other driver you mention so we can cross check?
Skylake driver is found within: /sound/soc/intel/skylake directory.
"SKL had limitations in FW" - that's misleading. This is neither FW issue nor HW 'limitation'. SKL is an older platform and its goals and design was different than say APL+. Basically, your needs do not align with what's present on SKL hw.
Czarek