2011/8/5 Mark Brown broonie@opensource.wolfsonmicro.com:
On Fri, Aug 05, 2011 at 04:00:52PM +0800, Scott Jiang wrote:
Why are you replying off-list? You should implement 16x8 SPI reads in the core stuff I'd expect, then disable cache for the CODEC.
Sorry, I just forgot to CC. I wonder if rbtree compress type can support this kind of sparse register?
Yes, rbtree works fine with this. You'd still take a hit on the size of your register defaults though.
And should the patch aginst 3.0 or 3.2?
3.0 can't be patched, though you could try submitting a patch to the stable guys. Probably best to start off with 3.1 and see where we go from there.
I got a problem here. As Takashi mentioned, our registers have a read/write bit in the upper 8bit. There are three methods: 1. pass different registers to snd_soc_read and snd_soc_write. But snd_kcontrol and snd_soc_dapm_widget can't work because I pass only one register. 2. deal with this bit in hw_read, but this will be deprecated by others whose chip doesn't have this bit. 3. I'd like to use SND_SOC_CUS type, but it has been removed since linux 3.0. I suggest we can reserve this type, considering SPI is a simple "de facto" standard.