On Wednesday 08 April 2009 01:14:05 ext Mark Brown wrote:
On Tue, Apr 07, 2009 at 08:19:11AM +0300, Peter Ujfalusi wrote:
twl4030: Samples the data on falling edge, shifts data out (and changes the FS) on rising edge tlv320aic23: Samples the data on rising, shifts data out (and changes the FS) on falling edge
What ASoC expects for DSP mode is that the data can be sampled on either the first (mode B) or second (mode A) rising edge of BCLK after a rising edge of LRCLK. This implies that the data should be driven on the falling edge of BCLK.
The TLV320AIC23 can do either mode - the description on page 24 matches exactly. Unless I'm missing something the inversion of the frame clock for osk5912 looks like a mistake. I'd need to read the code a bit more closely to check I've not missed something but it looks like the codec driver is never actually setting LRP so it's got the mode the wrong way round for the one it supports.
I have been also wondering about the missing LRP handling, but I do not have access to osk5912 board neither to tlv320aic32 codec...
The TWL4030 datasheet does not appear to be a model of clarity in this area but it looks awfully like mode A with an inverted bit clock (the data appears to be being driven rather than sampled on the rising edge but the first bit does start on the falling edge of the frame clock).
Well, in general there are lots of these kind of 'small' details missing from the documentation. One just have to try it out and see how it behaves ;)
This means the Beagle code looks about right unless I'm misreading something.
Does it means that the DSP_A addition is also correct? I have it drawn to paper, how the configuration in omap-mcbsp used by the beagle in 4 channel mode would look like, and it does look 100% as the TDM mode described in the twl datasheet...
BTW: when the twl is in 4 channel mode, it has to be the master on the bus (small thing, since twl usually is the master on the bus anyway)