-----Original Message----- From: Tudor Ambarus tudor.ambarus@linaro.org Sent: Friday, February 9, 2024 9:44 PM To: Mahapatra, Amit Kumar amit.kumar-mahapatra@amd.com; broonie@kernel.org; pratyush@kernel.org; miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com; sbinding@opensource.cirrus.com; lee@kernel.org; james.schulman@cirrus.com; david.rhodes@cirrus.com; rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; michael@walle.cc; linux-mtd@lists.infradead.org; nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com; claudiu.beznea@tuxon.dev; Simek, Michal michal.simek@amd.com; linux- arm-kernel@lists.infradead.org; alsa-devel@alsa-project.org; patches@opensource.cirrus.com; linux-sound@vger.kernel.org; git (AMD- Xilinx) git@amd.com; amitrkcian2002@gmail.com; Conor Dooley conor.dooley@microchip.com; beanhuo@micron.com Subject: Re: [PATCH v11 07/10] mtd: spi-nor: Add stacked memories support in spi-nor
On 2/9/24 11:06, Tudor Ambarus wrote:
On 12/21/23 06:54, Mahapatra, Amit Kumar wrote:
Something else to consider: I see that Micron has a twin quad mode: https://media-www.micron.com/- /media/client/global/documents/products/data-sheet/nor-flash/serial- nor/mt25t/generation-
b/mt25t_qljs_l_512_xba_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500
The micron's "Separate Chip-Select and Clock Signals" resembles the AMD's dual parallel 8-bit.
Yes, I agree.
Micron's "Shared Chip-Select and Clock Signals" differs from the AMD's stacked mode, as Micron uses DQ[3:0] and DQ[7:4], whereas AMD considers both as DQ[3:0].
Yes, correct.
Amit, please help me to assess this. I assume Micron and Microchip is using the same concepts as AMD uses for the "Dual Parallel 8-bit IO mode", but they call it "Twin Quad Mode".
I was wrong, the AMD datasheet [1] was misleading [2], it described the IOs for both flashes as IO[3:0], but later on in the "Table QSPI Interface Signals" the second flash is described with IO[7:4].
The AMD's 8-bit Dual Flash Parallel Interface is using dedicated CS# and CLK# lines for each flash. As Micron does, isn't it?
Micron says [3] that: "The device contains two quad I/O die, each able to operate independently for a total of eight I/Os. The memory map applies to each die. Each die has internal registers for status, configuration, and device protection that can be set and read independently from one
other.
Micron recommends that internal configuration settings for the two die be set identically."
Hello Tudor,
Amit,
I forgot to say my first conclusion about the quote from above. Even if the dies are in the same physical package, micron asks users to configure each die as it is a self-standing entity, IOW to configure each die as it is a flash on its own. To me it looks like 2 concatenated flashes at first look. Thus identical to how AMD controller works. Please clarify this.
That’s correct, the Micron flash that you referred can communicate with the AMD QSPI controller in both parallel and stacked mode.
it also says that: "When using quad commands in XIO-SPI or when using QIO-SPI, DQ[3:0]/DQ[7:4] are I/O."
and this would be a parallel concatenation of two flashes.
That's correct.
Regards, Amit
Then it would be good if you let us now the similarities and differences between how amd and mchp controller work, I scrawled few ideas below.
thanks, ta
So I guess the upper layers just ask for a chunk of memory to be written and the controller handles the cs# lines automatically. How is the AMD controller working, do you have to drive the cs# lines manually, or you just set the parallel mode and the controller takes care of
everything?
I assume this is how mchp is handling things, they seem to just set a bit the protocol into the QSPI_IFR.PROTTYP register field and that's all [4]. They even seem to write the registers of both flashes at the same
time.
In what regards the AMD's "dual stack interface", AMD is sharing the clock and IO lines and uses dedicated CS# lines for the flashes, whereas Micron shares the CS# and CLK# lines with different IO lines.
Amit, please study the architectures used by mchp, micron and amd and let us know if they are the same or they differ, and if they differ what are the differences.
I added Conor from mchp in cc, I see Nicolas is already there, and Bean from micron.
Thanks, ta
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/QSPI-Flash-Inter face-Signals [2]
https://docs.xilinx.com/viewer/attachment/dwmjhDJGICdJqD4swyVzcQ/fD8nv
4ry78xM0_EF5kv4mA [3] https://media-www.micron.com/-
/media/client/global/documents/products/
data-sheet/nor-flash/serial-nor/mt25t/generation-b/mt25t_qljs_l_512_xb a_0.pdf?rev=de70b770c5dc4da8b8ead06b57c03500 [4]
https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ Produ
ctDocuments/DataSheets/SAMA7G5-Series-Data-Sheet-DS60001765.pdf