On Mon, 30 Mar 2020 21:45:20 +0200, Cezary Rojewski wrote:
Update D0 <-> D3 sequence to correctly transition hardware and DSP core from and to D3. On top of that, set SHIM registers to their recommended defaults during D0 and D3 proceduces as HW does not reset registers for us.
Connected to: [alsa-devel][BUG] bdw-rt5650 DSP boot timeout https://mailman.alsa-project.org/pipermail/alsa-devel/2019-July/153098.html
[...]
Applied, thanks!
[1/1] ASoC: Intel: haswell: Power transition refactor commit: 8ec7d6043263ecf250b9b7c0dd8ade899487538a
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Thanks, Mark