On 09/13/2013 01:34 PM, Mark Brown wrote:
On Thu, Sep 12, 2013 at 03:10:12PM +0300, Jyri Sarha wrote:
On 2013-09-12 14:56, Mark Brown wrote:
What exactly is the dma register location here - what hardware is being controlled?
They is the McASP-bus receive/transmit buffer data port addresses. So those are McASP entity specific properties that need to be passed to DMA-engine.
OK, and presumably this is just part of the main McASP register block and doesn't need to go into DT?
Not really. For instance on am33xx SoCs the MPU usually accesses McASP registers trough L4 interconnect, which is not accessible by DMA controller. For DMA controller the data port is also mapped trough L3 bus to entirely different address and a simple register offset is not enough. Naturally this mapping may change SoC to SoC.
I have been working with OMAP family chips so long that I start think everybody would know their internal workings. Sorry about that.
Best regards, Jyri