15 May
2018
15 May
'18
9:36 a.m.
On Tue, 15 May 2018 08:40:54 +0200, Sriram Periyasamy wrote:
From: Pardha Saradhi K pardha.saradhi.kesapragada@intel.com
As per HW recommendation, after setting the RUN bit, software must read a 1 from the RUN bit, before modifying related control registers/re-starting the DMA engine.
Rather FIFO is checked in snd_hdac_stream_sync(), so I guess it already suffices. But we can add this sanity check there, too, if it really matters.
thanks,
Takashi