According to the datasheet:
Page0 / Register8: Audio Serial Data interface Control Register A BIT 7: Bit Clock Directional Control 0: Bit clock is an input (slave mode) 1: Bit clock is an output (master mode)
BIT 6: Word Clock Directional Control 0: Word clock is an input (slave mode) 1: Word clock is an output (master mode)
Current code sets BIT_CLK_MASTER and WORD_CLK_MASTER bits for master mode, but does not clear these bits for slave mode.
Signed-off-by: Axel Lin axel.lin@gmail.com --- sound/soc/codecs/tlv320aic3x.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index a77f6ea..14cb553 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1021,6 +1021,7 @@ static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, break; case SND_SOC_DAIFMT_CBS_CFS: aic3x->master = 0; + iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); break; default: return -EINVAL;