On Thu, Aug 11, 2011 at 02:32:53PM +0900, Mark Brown wrote:
On Thu, Aug 11, 2011 at 05:09:14AM +0200, Lars-Peter Clausen wrote:
On 08/11/2011 04:46 AM, Mark Brown wrote:
None of the current ASoC code will coalesce register writes at all, and in the case where you're doing writes to registers that aren't actually adjacent it's going to be marginal if it's better to transmit the intervening register or transmit another register address. That only really makes a difference during cache sync anyway.
I was think more in terms of in memory consumption and lookup time of the cache compared to a flat cache. If you have two blocks which have a gap of one register between them and that register gets inserted into the cache, ideally those two blocks would be merged, which doesn't seem to be the case currently. So instead of one rbnode with a block covering the whole register space you'll end up with a lot of smaller rbnodes.
Yes, that's true. I've got that in my TODO somewhere. It was not important enough during initial implementation.
Dimitris had done an initial version of the move of the cache over, though I didn't review it properly yet and he's on holiday now. I might repost it, there were a few issues but it's at least 90% of the way there IIRC from the time I had to look at it.
I'll be looking into this soon, there are a few issues to be resolved regarding the LZO code at the moment.
Thanks, Dimitris