On Mon, Jan 18, 2016 at 7:26 AM, Arnaud Mouiche arnaud.mouiche@invoxia.com wrote:
im6sl reference manual 47.7.4: " Bit clock - Used to serially clock the data bits in and out of the SSI
port.
This clock is either generated internally (from SSI's sys clock) or taken from external clock source (through the Tx/Rx clock ports). [...] Care should be taken to ensure that the bit clock frequency (either internally generated by dividing the SSI's sys clock or sourced from external device through Tx/Rx clock ports) is never greater than 1/5 of the ipg_clk (from CCM) frequency. "
Since, in master mode, the sysclk is a multiple of bitclk, we can easily reach a high sysclk value, whereas keeping a reasonable bitclk.
ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1) yet ipg_clk/5 = 66Mhz/5 = 13.2
Signed-off-by: Arnaud Mouiche arnaud.mouiche@invoxia.com
sound/soc/fsl/fsl_ssi.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index cfc78b8..dbd5f10 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -679,6 +679,15 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream
*substream,
if (IS_ERR(ssi_private->baudclk)) return -EINVAL;
/** Hardware limitation: The bclk rate must be* never greater than 1/5 IPG clock rate*/if (freq * 5 > clk_get_rate(ssi_private->clk)) {dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");return -EINVAL;}baudclk_is_used = ssi_private->baudclk_streams &
~(BIT(substream->stream));
/* It should be already enough to divide clock by setting pm
alone */
@@ -695,13 +704,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream
*substream,
else clkrate = clk_round_rate(ssi_private->baudclk,
tmprate);
/** Hardware limitation: The bclk rate must be* never greater than 1/5 IPG clock rate*/if (clkrate * 5 > clk_get_rate(ssi_private->clk))continue;clkrate /= factor; afreq = clkrate / (i + 1);-- 1.9.1
Tested-By: Caleb Crome caleb@crome.org Reviewed-"By: Caleb Crome caleb@crome.org