27 Jan
2017
27 Jan
'17
1:22 a.m.
On 01/23, Pierre-Louis Bossart wrote:
From: Irina Tirdea irina.tirdea@intel.com
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC).
The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them.
Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea
Signed-off-by: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com Signed-off-by: Irina Tirdea irina.tirdea@intel.com
Applied to clk-next
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