On Wed, May 24, 2023 at 11:12:49AM -0500, Chris Morgan wrote:
On Wed, May 24, 2023 at 12:57:02PM +0100, Mark Brown wrote:
The other constraints have separate rates and ratios, with wildly different values between the two - the ratio (I'm guessing a clock divider) being written to a 5 bit field which obviously can't contain the actual sample rate.
A bit over my head here, I saw this patch from the Rockchip BSP kernel branch and tested it on my mainline kernel. Long story short the clock for the mclk is 12000000. I see that there are similar issues for the ES8316 on the Rock 5B, so I will probably just wait for a proper fix there and then implement something similar here.
It sounded from the rest of the series like you don't actually want to run at 12MHz anyway, you want a change which deconfigures the sysclk when the card is idle - that'd allow it to be reconfigured as needed to support the widest possible set of rates. That'd be work in the generic cards.