From: Mengdong Lin mengdong.lin@intel.com
For Baytrail (Valleyview) and Braswell (Cherryview), not the HD-A controller but only the display codec is in the shared power well with gfx.
Signed-off-by: Mengdong Lin mengdong.lin@intel.com
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 1b688ba..e73dc34 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1903,8 +1903,9 @@ static int azx_probe_continue(struct azx *chip) * display codec needs the power and it can be released after probe. */ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { - /* Assume the controller needs the power by default */ - chip->need_i915_power = 1; + /* Baytral/Braswell controllers don't need this power */ + if (pci->device != 0x0f04 && pci->device != 0x2284) + chip->need_i915_power = 1;
#ifdef CONFIG_SND_HDA_I915 err = hda_i915_init(hda); diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index 5f44f60..7b2744c 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -2335,6 +2335,14 @@ static int patch_generic_hdmi(struct hda_codec *codec) intel_haswell_fixup_enable_dp12(codec); }
+ /* For Valleyview/Cherryview, the codec is in the display power well. + * For Haswell/Broadwell, the controller is also in the power well and + * can cover codec power request, and so need not set this flag. + * For previous platforms, there is no such power well feature. + */ + if (is_valleyview_plus(codec)) + codec->core.need_i915_power = 1; + if (is_haswell_plus(codec) || is_valleyview_plus(codec)) codec->depop_delay = 0;