1 Jul
2013
1 Jul
'13
12:11 p.m.
On Mon, Jul 01, 2013 at 04:16:10PM +0800, Shawn Guo wrote:
Mostly the mxs system design uses saif0 mclk output as the clock source of codec. Since the mclk is implemented as a general divider with the saif clk as the parent clock, let's register the mclk as a basic clk-divider to common clock framework. Then with it being a clock provdier, clk_get() call in codec driver probe function will just work.
Applied, thanks.