On 28/03/2022 08:14, Sameer Pujar wrote:
The rt5658 or rt5659 CODEC system clock (SYSCLK) can be derived from various clock sources. For example it can be derived either from master clock (MCLK) or by internal PLL. The internal PLL again can take input clock references from bit clocks (BCLKs) and MCLK. To enable a flexible clocking configuration the DT binding is extended here.
It makes use of standard clock bindings and sets up the clock relation via DT.
Signed-off-by: Sameer Pujar spujar@nvidia.com Cc: Oder Chiou oder_chiou@realtek.com
.../devicetree/bindings/sound/realtek,rt5659.yaml | 53 ++++++++++++++++++++-- 1 file changed, 49 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml index b0485b8..0c2f3cb 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml @@ -29,12 +29,28 @@ properties: maxItems: 1
clocks:
- items:
- description: Master clock (MCLK) to the CODEC
description: |
CODEC can receive multiple clock inputs like Masterclock (MCLK), I2S bit clocks (BCLK1, BCLK2, BCLK3,BCLK4). The CODEC SYSCLK can be generated from MCLKor internal PLL. In turn PLL can reference from MCLKand BCLKs.clock-names:
- items:
- const: mclk
- description: |
The clock names can be combination of following:"mclk" : Master clock"pll_ref" : Reference to CODEC PLL clock"sysclk" : CODEC SYSCLK"^bclk[1-4]$" : Bit clocks to CODEC
No, that does not look correct. You allow anything as clock input (even 20 clocks, different names, any order). That's not how DT schema should work and that's not how hardware looks like.
Usually the clock inputs are always there which also you mentioned in description - "multiple clock inputs". All these clocks should be expected, unless really the wires (physical wires) can be left disconnected.
Best regards, Krzysztof