From: Colin Ian King colin.king@canonical.com
Currently, the comparison of div < 0 is always false because div is an unsigned int. Fix this by making div an int.
Detected by CoverityScan, CID#1475309 ("Unsigned compared against 0")
Fixes: 8307b2afd386 "(ASoC: stm32: sai: set sai as mclk clock provider") Signed-off-by: Colin Ian King colin.king@canonical.com --- sound/soc/stm/stm32_sai_sub.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/sound/soc/stm/stm32_sai_sub.c b/sound/soc/stm/stm32_sai_sub.c index 211589b0b2ef..d4825700b63f 100644 --- a/sound/soc/stm/stm32_sai_sub.c +++ b/sound/soc/stm/stm32_sai_sub.c @@ -336,8 +336,7 @@ static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, { struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); struct stm32_sai_sub_data *sai = mclk->sai_data; - unsigned int div; - int ret; + int div, ret;
div = stm32_sai_get_clk_div(sai, parent_rate, rate); if (div < 0)