22 Apr
2023
22 Apr
'23
5:36 p.m.
On Sat, 22 Apr 2023 15:24:30 +0200, Oswald Buddenhagen wrote:
Unlike the Alice2 chips used on 1st generation E-MU cards, the Tina/Tina2 chips used on the 2nd gen cards have only six GPIN pins, which means that we need to use a smaller mask. Failure to do so would falsify the read data if the FPGA tried to raise an IRQ right at that moment. This wasn't a problem so far, as we didn't actually enable FPGA IRQs, but that's going to change soon.
Signed-off-by: Oswald Buddenhagen oswald.buddenhagen@gmx.de
v2:
- added description
This is *MUCH* better and helpful to understand the changes.
Applied now. Thanks!
Takashi