On Fri, Nov 21, 2008 at 12:01 PM, Mark Brown broonie@sirena.org.uk wrote:
On Fri, Nov 21, 2008 at 10:45:46AM +0100, John Kacur wrote:
Where are dma overflow interrupts handled? For example I don't see this in sound/soc/s3c24xx-i2s.c
The s3c24xx ASoC code doesn't interact with the DMA controller directly, it uses the DMA API exported by the arch/arm code to do that.
Ok, thanks, I found that s3c2410_dma_request registers 3c2410_dma_irq. (in arch/arm/plat-s3c24xx/dma.c) I see other platforms like omap register an interrupt handler in the pcm code when they do a dma request.
My scenario is this, the dma controller will be writing to the i2s transmission fifo register (called I2SxTXFDAT on my platform - Jade). If an overflow occurs an interrupt is generated. Among other tasks my interrupt handler will have to clear a status bit in an i2s register. I was thinking I need to somehow have my interrupt handler in my pcm code, although conceptually it seems like an i2s thing.
If you have any hints for how I should design / implement this it would be appreciated. I read the documentation on-line http://www.kernel.org/pub/linux/kernel/people/tiwai/docs/writing-an-alsa-dri... but it doesn't quite seem to match my scenario.
Thanks