Hi
Sounds like a bug to me...should fix it first by marking the data registers as volatile.
The ETDR is a writable register, it is not volatile. Even we change it to Volatile, I don't think we can't avoid this issue. for the regcache_sync Just to write this register, it is correct behavior.
Is that so? Quoting the comments of regcache_sync(): "* regcache_sync - Sync the register cache with the hardware.
- @map: map to configure.
- Any registers that should not be synced should be marked as
- volatile."
If regcache_sync() does sync volatile registers too as you said, I don't mind having this FIFO reset WAR for now, though I think this mismatch between the comments and the actual behavior then should
get people's attention.
Thank you
ETDR is not volatile, if we mark it is volatile, is it correct?
Well, you have a point -- it might not be ideally true, but it sounds like a correct fix to me according to this comments.
We can wait for Mark's comments or just send a patch to the mail list for review.
Thanks you
I test this patch, we don't need to reset the FIFO, and regcache_sync didn't Write the ETDR even the EDTR is not volatile. This fault maybe caused by Legacy, in the beginning we add this patch in internal branch, there maybe Something cause this issue, but now can't reproduced.
So I will remove the reset of FIFO.
Best regards Wang Shengjiu