The rt5658 or rt5659 CODEC system clock (SYSCLK) can be derived from various clock sources. For example it can be derived either from master clock (MCLK) or by internal PLL. The internal PLL again can take input clock references from bit clocks (BCLKs) and MCLK. To enable a flexible clocking configuration the DT binding is extended here.
It makes use of standard clock bindings and sets up the clock relation via DT.
Signed-off-by: Sameer Pujar spujar@nvidia.com Cc: Oder Chiou oder_chiou@realtek.com --- .../devicetree/bindings/sound/realtek,rt5659.yaml | 53 ++++++++++++++++++++-- 1 file changed, 49 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml index b0485b8..0c2f3cb 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml @@ -29,12 +29,28 @@ properties: maxItems: 1
clocks: - items: - - description: Master clock (MCLK) to the CODEC + description: | + CODEC can receive multiple clock inputs like Master + clock (MCLK), I2S bit clocks (BCLK1, BCLK2, BCLK3, + BCLK4). The CODEC SYSCLK can be generated from MCLK + or internal PLL. In turn PLL can reference from MCLK + and BCLKs.
clock-names: - items: - - const: mclk + description: | + The clock names can be combination of following: + "mclk" : Master clock + "pll_ref" : Reference to CODEC PLL clock + "sysclk" : CODEC SYSCLK + "^bclk[1-4]$" : Bit clocks to CODEC + + "#clock-cells": + const: 1 + + clock-output-names: + description: PLL output clock + $ref: /schemas/types.yaml#/definitions/string + const: rt5659_pll_out
realtek,in1-differential: description: MIC1 input is differntial and not single-ended. @@ -97,6 +113,7 @@ required:
examples: - | + /* SYSCLK derived from MCLK */ #include<dt-bindings/gpio/tegra194-gpio.h> #include<dt-bindings/clock/tegra194-clock.h>
@@ -114,3 +131,31 @@ examples: realtek,jd-src = <2>; }; }; + + - | + /* + * SYSCLK is derived from CODEC internal PLL and PLL uses I2S1 BCLK + * as the clock reference. + */ + #include<dt-bindings/gpio/tegra194-gpio.h> + #include<dt-bindings/clock/tegra194-clock.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rt5658: audio-codec@1a { + compatible = "realtek,rt5658"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA194_MAIN_GPIO(S, 5) GPIO_ACTIVE_HIGH>; + clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>, + <&bpmp TEGRA194_CLK_I2S1>, + <&bpmp TEGRA194_CLK_I2S1>, + <&rt5658 0>; + clock-names = "mclk", "bclk1", "pll_ref", "sysclk"; + #clock-cells = <1>; + clock-output-names = "rt5659_pll_out"; + realtek,jd-src = <2>; + }; + };