Hi Jarkko,
On 03/16/2012 09:00 AM, Jarkko Nikula wrote:
Out of curiosity, I guess this will decrease a memory bus or DMA controller load a bit.
Yes it will slightly decrease the load on those. It will also decrease the number of DMA requests going from McBSP to the sDMA controller.
Can you see any difference with the SW tools (top, etc) under some system load or do you need some on-chip observability to be able to measure effect of this transfer pattern change?
I can not see difference between the old element/packet-element/threshold mode from user space point of view. I think the effect can be seen in an optimized system more. The decreased load on SDRAM/sDMA should help with the performance, less DMA request means less frequent activity, which should decrease power consumption.
Other good thing might be is that now the DMA moves in sample steps, and not in words.