13 Sep
2023
13 Sep
'23
9:50 a.m.
This is not dependent on a specific vendor, but is intended to describe the properties of the signal(single/burst request) connection relationship between i2s and dma.
How does this relationship depend on hardware?
When designing a SoC, it depends on the RTL and Bus connection. My company has two types of configuration SoC: single and burst to meet ASIC customer's requirements.
Thanks, myunguk