23 Aug
2012
23 Aug
'12
8:48 a.m.
On Thu, Aug 23, 2012 at 02:41:30PM +0800, George Stefan wrote: ...
/*set the saif clk mux, saif0/saif1 both use saif0 clk*/ __raw_writel(BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(0x0), \
Should this be 0x2 if both saif0 and saif1 are using saif0 clk?
IO_ADDRESS(DIGCTL_PHYS_ADDR) + HW_DIGCTL_CTRL); Using this configuration i am not able to receive IRQs from DMA and i think the reason is that SAIF is not receiving the CLK. What do you think? Thanks, George.
Regards Dong Aisheng