18 Sep
2013
18 Sep
'13
4:39 p.m.
On Tue, Sep 17, 2013 at 12:26:02PM +0300, jsarha@ti.com wrote:
From: Jyri Sarha jsarha@ti.com
This patch adds DMA register location to mcasp DT bindings. On am33xx SoCs the McASP registers are mapped trough L4 interconnect, which is not accessible by the DMA controller, so McASP data port is mapped trough L3 to a different location.
Looks good to me but again you ought to CC the DT maintainers directly.