Checking TE and RE bits in SCR register doesn't work for AC97 mode which enables SSIEN, TE and RE in the fsl_ssi_setup_ac97() that's called during probe().
So when running into the trigger(), it will always get the result of both TE and RE being enabled already, even if actually there is no active stream.
This patch fixes this issue by adding a variable to log the active streams manually.
Signed-off-by: Nicolin Chen nicoleotsuka@gmail.com Tested-by: Caleb Crome caleb@crome.org --- Changelog v3 * Replaced "bool dir" with "int dir" v2 * Replaced bool tx with bool dir
sound/soc/fsl/fsl_ssi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 8984ee2..51e7405 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -205,6 +205,7 @@ struct fsl_ssi_soc_data { * @cpu_dai_drv: CPU DAI driver for this device * * @dai_fmt: DAI configuration this device is currently used with + * @streams: Mask of current active streams: BIT(TX) and BIT(RX) * @i2s_net: I2S and Network mode configurations of SCR register * @use_dma: DMA is used or FIQ with stream filter * @use_dual_fifo: DMA with support for dual FIFO mode @@ -249,6 +250,7 @@ struct fsl_ssi { struct snd_soc_dai_driver cpu_dai_drv;
unsigned int dai_fmt; + u8 streams; u8 i2s_net; bool use_dma; bool use_dual_fifo; @@ -444,15 +446,14 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, struct fsl_ssi_regvals *vals) { + int dir = (&ssi->regvals[TX] == vals) ? TX : RX; struct regmap *regs = ssi->regs; struct fsl_ssi_regvals *avals; int nr_active_streams; - u32 scr; int keep_active;
- regmap_read(regs, REG_SSI_SCR, &scr); - - nr_active_streams = !!(scr & SSI_SCR_TE) + !!(scr & SSI_SCR_RE); + nr_active_streams = !!(ssi->streams & BIT(TX)) + + !!(ssi->streams & BIT(RX));
if (nr_active_streams - 1 > 0) keep_active = 1; @@ -474,6 +475,9 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, keep_active); /* Safely disable SCR register for the stream */ regmap_update_bits(regs, REG_SSI_SCR, scr, 0); + + /* Log the disabled stream to the mask */ + ssi->streams &= ~BIT(dir); }
/* @@ -549,6 +553,9 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, } /* Enable all remaining bits */ regmap_update_bits(regs, REG_SSI_SCR, vals->scr, vals->scr); + + /* Log the enabled stream to the mask */ + ssi->streams |= BIT(dir); } }