On Tue, May 3, 2016 at 5:23 AM, Fabio Estevam festevam@gmail.com wrote:
On Tue, May 3, 2016 at 9:13 AM, Arnaud Mouiche arnaud.mouiche@invoxia.com wrote:
im6sl reference manual 47.7.4: " Bit clock - Used to serially clock the data bits in and out of the SSI port. This clock is either generated internally (from SSI's sys clock) or taken from external clock source (through the Tx/Rx clock ports). [...] Care should be taken to ensure that the bit clock frequency (either internally generated by dividing the SSI's sys clock or sourced from external device through Tx/Rx clock ports) is never greater than 1/5 of the ipg_clk (from CCM) frequency. "
Since, in master mode, the sysclk is a multiple of bitclk, we can easily reach a high sysclk value, whereas keeping a reasonable bitclk.
ex: 8ch x 16bit x 48kHz = 6144000, requires a 24576000 sysclk (PM=1) yet ipg_clk/5 = 66Mhz/5 = 13.2
Signed-off-by: Arnaud Mouiche arnaud.mouiche@invoxia.com
Reviewed-by: Fabio Estevam fabio.estevam@nxp.com
Tested-by: Caleb Crome caleb@crome.org