Hi Clemens,
On Dec 12 2015 20:42, Clemens Ladisch wrote:
Takashi Sakamoto wrote:
Some users have reported that their Dice based models generate packet discontinuity at the beginning of streaming. When standing on an assumption that the value of SYT field in transferred AMDTP packet comes from phase lock circuit, this comes from phase unlocking with current clock source. Just waiting for dice notification is not enough to prevent from packet discontinuity.
This commit checks the register of phase lock after clock state change for this purpose.
Is this patch actually known to help?
This discontinuity could also come from an unexpected initial DBC value. I think it would be a good idea to unconditionally enable CIP_SKIP_INIT_DBC_CHECK for all devices.
This issue also occurs on my ImpactTwin. Today, I dropped this patch and tried re-generate this issue, then I cannot regenerate it.
As long as I tested, the deferred registration has an effect for this issue. I guess that the beginning of packet streaming is envolved to the end of hardware initialization, then discontinuity occurs.
I decide to drop this patch from next post, thanks to address it.
Regards
Takashi Sakamoto