Re: [alsa-devel] PLL computation in TLV320AIC3x SoC driver

On Tue, 2009-12-08 at 12:28 +0100, Peter Meerwald wrote:

Hello,

I'm trying to use the SoC TLV320AIC3x codec driver with sysclk 16384000 and ran into some problems with setting PLL; below is a patch against linux-2.6-asoc

note that the original code uses variables pll_r and pll_p instead of the loop variable r and p to compute tmp, this seems broken

further, the original code does not respect the constraints on j (>= 4, <= 55 for d==0) according to the codec's datasheet, and similarly for d!=0

I've tested the code with a number of reasonable sysclk values and got sane PLL values; please apply if acceptable

Can you confirm you also tested against 12.288MHz and 11.2869MHz ?

If so, Acked-by: Liam Girdwood lrg@slimlogic.co.uk

Thanks

Liam