On Thu, Dec 21, 2017 at 08:10:07AM -0800, Caleb Crome wrote:
the mainline tree, I would like to treat this mail as a separate
bug report and fix it with a separate patch.
warn: 11a0 11a1 1160 11a3 11a4 11a5 11a6 11a7
warn: Valid frame after 1 invalid frames
warn: 11c0 11c1 11c2 11c3 11c4 11c5 11c6 11c7
warn: first invalid frame while expecting frame 0x00a0
warn: 13e7 1400 1401 1402 1403 1404 1405 1404
warn: 1407 1420 1421 1422 1423 1424 1425 1426
warn: 1427 1440 1441 1442 1443 1444 1445 1484
warn: 1447 1460 1461 1462 1463 1464 1465 1466
Those last 4 lines are the channel slips -- the least significant
nibble should be the channel number: i.e. should go 0, 1, 2, 3, 4, 5,
6, 7.
Ugh, so it's basically quite broken again -- before these patches.
Okay, operator error on my part. There was an old clock setting in my ssi3 dtsi file that (falsely) modified the ssi baud clock frequency. Nicolin's patch
ASoC: fsl_ssi: Caculate bit clock rate using slot number and widthnow properly computes the master clock, and the old dtsi settings that were necessary to fake things into the right speed are now obsolete.
So... basically, everything is back to working properly. it wasn't broken at all -- just my oversight on a ssi clock setting in the dtb.
Well, that's a good news :) Thanks for the efforts during these days to track back every corner.
Happy holiday. Nicolin