23 Aug
2021
23 Aug
'21
2:12 p.m.
On 18-08-21, 11:01, Bard Liao wrote:
From: Pierre-Louis Bossart pierre-louis.bossart@linux.intel.com
The duration of the hw_reset is defined as 4096 cycles. The Cadence IP allows for an additional delay which doesn't seem necessary in practice: the actual reset sequence duration is defined by the sync_go mechanism, not by the IP itself.
Applied, thanks
--
~Vinod