7 Sep
2012
7 Sep
'12
3:51 a.m.
On Thu, Sep 06, 2012 at 05:47:33PM -0600, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
The I2S controllers are programmed with an "attention" level of 4 DWORDs. This must match the configuration passed to the DMA driver, so that when they burst in data, they don't overflow the available FIFO space. Also, the burst size is relevant to the destination for playback, and source for capture, not vice-versa as originally written.
Applied, thanks.