On Wed, Jan 20, 2021 at 12:41:18PM +1300, Eliot Blennerhassett wrote:
It would be a bit easier to have one discussion per mail rather than mixing several different topics in a single mail, you should also CC the maintainers for the relevant drivers so they can comment on any issues in their drivers. I've copied in a bunch of people for the Freescale drivers and gpiolib.
- Reset polarity of ak4458.
When imx-ak4458 is used, the platform driver handles the codec reset specified in DT compatible = "fsl,imx-audio-ak4458"; ak4458,pdn-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
Used here. Afaics gpio_set_value sets the raw value given, ignoring the polarity specified by the DT?
This is supposed to be handled by gpiolib I thought, I don't know off the top of my head if you need to convert the driver to use descriptors rather than numbers for that to happen. It's obviously not ideal if we force all drivers to implement custom inversion logic.
- Clock rate setting with simple-card
When simple-card is used and DT specifies mclk fs: simple-audio-card,mclk-fs = <256>;
asoc_simple_hw_params() calls snd_soc_dai_set_sysclk(..., clk_id=0, ...)
The hard-coded clk_id=0 doesn't work with fsl-sai, which requires clk_id==1.
For my testing purposes I changed the hard-coded value, but I think the proper solution could be to add a DT property to specify the clk_id (default=0) ?
That would make the clock an ABI. If it's getting to the point of needing to specify multiple clocks then we really should be looking at using the clock bindings to specify which one to use, that's a bit involved though.
- Memory mapped stream access by aplay does not work.
This precludes use of alsa plugins e.g. dmix
I have found no reason or solution for this so far
In what way does it not work - what errors or other problems do you see?
- Unable to get multiple source clocks working with fsl-sai
With a single assigned-clock, switching between 48k and 44k1 clock rate families is accomplished by reparenting the root clock to the appropriate audio pll clock.
&sai2 { assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clocks = <&clk IMX8MM_CLK_SAI2>; assigned-clock-rates = <12288000>; ... };
However if two of the sai mclks could be set to 48k and 44k1 derived rates respectively, the clock reparenting would not be required, and fsl_sai_set_bclk() would search the mclks and choose the appropriate mclk for the requested rate.
DT would be something like this:
&sai2 { assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; assigned-clocks = <&clk IMX8MM_CLK_SAI2>, <&clk IMX8MM_CLK_SAI1>; assigned-clock-rates = <12288000>, <11289600>; };
This setup doesn't work as I hoped it would, don't know why not.
regards
-- Eliot Blennerhassett