Re: [PATCH v4 5/5] pinctrl: qcom: Add SC7280 lpass pin configuration

On Fri 03 Dec 05:32 CST 2021, Srinivasa Rao Mandadapu wrote:

From: Srinivasa Rao Mandadapu srivasam@codeaurora.org

Add pin control support for SC7280 LPASS LPI.

Signed-off-by: Srinivasa Rao Mandadapu srivasam@codeaurora.org Co-developed-by: Venkata Prasad Potturu potturu@codeaurora.org Signed-off-by: Venkata Prasad Potturu potturu@codeaurora.org

---

drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 169 ++++++++++++++++++++++++ 3 files changed, 178 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index e750e10..37fe868 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -328,4 +328,12 @@ config PINCTRL_SM8250_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM8250 platform.

+config PINCTRL_SC7280_LPASS_LPI

• tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"

You misspelled SC7280 here.

• depends on PINCTRL_LPASS_LPI
• help

•  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  

•  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
  

•  (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
  

endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 8bc877e..6c3ddaf 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o +obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o

Please keep these entries sorted alphabetically, same with Kconfig.

Regards, Bjorn

diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c new file mode 100644 index 0000000..94bec15 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
• • ALSA SoC platform-machine driver for QTi LPASS
• */

+#include <linux/clk.h> +#include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h>

+#include "pinctrl-lpass-lpi.h"

+enum lpass_lpi_functions {

• LPI_MUX_dmic1_clk,
• LPI_MUX_dmic1_data,
• LPI_MUX_dmic2_clk,
• LPI_MUX_dmic2_data,
• LPI_MUX_dmic3_clk,
• LPI_MUX_dmic3_data,
• LPI_MUX_i2s1_clk,
• LPI_MUX_i2s1_data,
• LPI_MUX_i2s1_ws,
• LPI_MUX_i2s2_clk,
• LPI_MUX_i2s2_data,
• LPI_MUX_i2s2_ws,
• LPI_MUX_qua_mi2s_data,
• LPI_MUX_qua_mi2s_sclk,
• LPI_MUX_qua_mi2s_ws,
• LPI_MUX_swr_rx_clk,
• LPI_MUX_swr_rx_data,
• LPI_MUX_swr_tx_clk,
• LPI_MUX_swr_tx_data,
• LPI_MUX_wsa_swr_clk,
• LPI_MUX_wsa_swr_data,
• LPI_MUX_gpio,
• LPI_MUX__,

+};

+static const unsigned int gpio0_pins[] = { 0 }; +static const unsigned int gpio1_pins[] = { 1 }; +static const unsigned int gpio2_pins[] = { 2 }; +static const unsigned int gpio3_pins[] = { 3 }; +static const unsigned int gpio4_pins[] = { 4 }; +static const unsigned int gpio5_pins[] = { 5 }; +static const unsigned int gpio6_pins[] = { 6 }; +static const unsigned int gpio7_pins[] = { 7 }; +static const unsigned int gpio8_pins[] = { 8 }; +static const unsigned int gpio9_pins[] = { 9 }; +static const unsigned int gpio10_pins[] = { 10 }; +static const unsigned int gpio11_pins[] = { 11 }; +static const unsigned int gpio12_pins[] = { 12 }; +static const unsigned int gpio13_pins[] = { 13 }; +static const unsigned int gpio14_pins[] = { 14 };

+/* sc7280 variant specific data */ +static const struct pinctrl_pin_desc sc7280_lpi_pins[] = {

• PINCTRL_PIN(0, "gpio0"),
• PINCTRL_PIN(1, "gpio1"),
• PINCTRL_PIN(2, "gpio2"),
• PINCTRL_PIN(3, "gpio3"),
• PINCTRL_PIN(4, "gpio4"),
• PINCTRL_PIN(5, "gpio5"),
• PINCTRL_PIN(6, "gpio6"),
• PINCTRL_PIN(7, "gpio7"),
• PINCTRL_PIN(8, "gpio8"),
• PINCTRL_PIN(9, "gpio9"),
• PINCTRL_PIN(10, "gpio10"),
• PINCTRL_PIN(11, "gpio11"),
• PINCTRL_PIN(12, "gpio12"),
• PINCTRL_PIN(13, "gpio13"),
• PINCTRL_PIN(14, "gpio14"),

+};

+static const char * const swr_tx_clk_groups[] = { "gpio0" }; +static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; +static const char * const swr_rx_clk_groups[] = { "gpio3" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] = { "gpio6" }; +static const char * const dmic1_data_groups[] = { "gpio7" }; +static const char * const dmic2_clk_groups[] = { "gpio8" }; +static const char * const dmic2_data_groups[] = { "gpio9" }; +static const char * const i2s2_clk_groups[] = { "gpio10" }; +static const char * const i2s2_ws_groups[] = { "gpio11" }; +static const char * const dmic3_clk_groups[] = { "gpio12" }; +static const char * const dmic3_data_groups[] = { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; +static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; +static const char * const i2s1_clk_groups[] = { "gpio6" }; +static const char * const i2s1_ws_groups[] = { "gpio7" }; +static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] = { "gpio10" }; +static const char * const wsa_swr_data_groups[] = { "gpio11" }; +static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };

+static const struct lpi_pingroup sc7280_groups[] = {

• LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
• LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
• LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
• LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
• LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
• LPI_PINGROUP(5, 12, swr_rx_data, _, _, _),
• LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
• LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
• LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
• LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
• LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
• LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
• LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
• LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
• LPI_PINGROUP(14, 6, swr_tx_data, _, _, _),

+};

+static const struct lpi_function sc7280_functions[] = {

• LPI_FUNCTION(dmic1_clk),
• LPI_FUNCTION(dmic1_data),
• LPI_FUNCTION(dmic2_clk),
• LPI_FUNCTION(dmic2_data),
• LPI_FUNCTION(dmic3_clk),
• LPI_FUNCTION(dmic3_data),
• LPI_FUNCTION(i2s1_clk),
• LPI_FUNCTION(i2s1_data),
• LPI_FUNCTION(i2s1_ws),
• LPI_FUNCTION(i2s2_clk),
• LPI_FUNCTION(i2s2_data),
• LPI_FUNCTION(i2s2_ws),
• LPI_FUNCTION(qua_mi2s_data),
• LPI_FUNCTION(qua_mi2s_sclk),
• LPI_FUNCTION(qua_mi2s_ws),
• LPI_FUNCTION(swr_rx_clk),
• LPI_FUNCTION(swr_rx_data),
• LPI_FUNCTION(swr_tx_clk),
• LPI_FUNCTION(swr_tx_data),
• LPI_FUNCTION(wsa_swr_clk),
• LPI_FUNCTION(wsa_swr_data),

+};

+static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {

• .pins = sc7280_lpi_pins,
• .npins = ARRAY_SIZE(sc7280_lpi_pins),
• .groups = sc7280_groups,
• .ngroups = ARRAY_SIZE(sc7280_groups),
• .functions = sc7280_functions,
• .nfunctions = ARRAY_SIZE(sc7280_functions),

+};

+static const struct of_device_id lpi_pinctrl_of_match[] = {

• {

•       .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
  

•       .data = &sc7280_lpi_data,
  

• },
• { }

+}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);

+static struct platform_driver lpi_pinctrl_driver = {

• .driver = {

•    .name = "qcom-sc7280-lpass-lpi-pinctrl",
  

•    .of_match_table = lpi_pinctrl_of_match,
  

• },
• .probe = lpi_pinctrl_probe,
• .remove = lpi_pinctrl_remove,

+};

+module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL");

-- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.