On Tue, 14 Sep 2010 13:21:39 +0100 Mark Brown broonie@opensource.wolfsonmicro.com wrote:
On Tue, Sep 14, 2010 at 03:14:45PM +0300, Jarkko Nikula wrote:
Mark Brown broonie@opensource.wolfsonmicro.com wrote:
It'd be a bit nicer to do this by using snd_soc_read() here also and marking the registers as volatile. This makes the process much less error prone since users can just use snd_soc_read() and the register cache code will work out if it needs to go to the chip or not.
Actually I looked that but problem with aic3x is that most of the volatile bits are with r/w configuration bits in the same registers. There are a few completely volatile read-only registers but currently there is no use for them.
Oh, so you would essentially kill the cache? Sad. It'd be nice to put comments somewhere in the driver noting this to discourage people doing the change.
Well cache is then out of sync with regarding of those gpio & headset detect bits here but there wasn't use for them elsewhere so at the moment it looks like null-op to write value to cache.
But is it marking register as volatile due 1-2 bits causing more problems if we don't cache rest of the r/w bits?