On Fri, Apr 18, 2008 at 12:38 PM, Daniel Mack daniel@caiaq.org wrote:
On Fri, Apr 18, 2008 at 11:58:49AM +0300, Jarkko Nikula wrote:
Ok, now I see. Probably you should refer it as, at least in comment,
128*Q
instead of 256 eventhough the driver is not currently touching the Q
value
in AIC3X_PLL_PROGA_REG.
Well, the constraint for that condition is that MCLK = 256*WCLK, and the reason why that works for the chip without PLL is that Q=2. I stated that a little better in the attached patch.
I would rather refer there just "Fsref = CLKDIV_IN / (128*Q)" as the condition where PLL can be disabled (or is mandatory where it must be disabled?).
Referring to data sheet page 27 is not good as it's correct only for certain version of AIC33 spec and driver supports other AIC3x chips as well :-)
Are you sure this is a general case?
Well, the reset default is 0 (as stated on page 44) and set_hw_params() is the only location where this value is written. So if it's never written with a different value, it should always be set to its default, no?
I mean even if the I2S interface Fs meets the MCLK/256 condition, the audio sample rate may be lower and it may be still required to set ADC and DAC rates.
Jarkko