On 22/02/2023 12:39, Chancel Liu wrote:
This property specifies power up to audio out time. It's necessary beacause this device has to wait some time before ready to output audio
typo... run spellcheck, also on the subject
after MCLK, BCLK and MUTE=1 are enabled. For more details about the timing constraints, please refer to WTN0302 on
Signed-off-by: Chancel Liu chancel.liu@nxp.com
.../devicetree/bindings/sound/wlf,wm8524.yaml | 10
++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml
b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml
index 09c54cc7de95..54b4da5470e4 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml @@ -21,6 +21,15 @@ properties: description: a GPIO spec for the MUTE pin.
- wlf,power-up-delay-ms:
- maximum: 1500
maximum is 1003. Where do you see 1500?
minimum: 82
Yes, you are absolutely right. From the power up to audio out timing table in WTN0302, the minimum number is 82 and the maximum is 1003.
Consider the following possibilities: 1. These timings may depend on the system design 2. These timings may be simulated results 3. These timings may be the minimum values
I set a larger value trying to extend the time. The larger value of course introduces unwanted time delay but it benefits on avoiding beginning audio lost.
I also did some tests on a board. If I want to work on 48KHZ sample rate and 512FS, the recommended value is 143. But the test result showed 143ms is not enough. I increased the value to 500ms and could hear the beginning sound.
Maybe it's a better choice to let DT set the suitable value? Is there a similar situation before?
- default: 100
- description:
Power up sequency delay time in millisecond. It specifies power up to
typo: sequence?
Sorry. I must avoid these spelling mistakes.
audio out time. For more details about the timing constraints of this
device, please refer to WTN0302 on
According to WTN0302 this might or might not include regulator ramp-up-delay. You should clearly indicate which part of it this delay is to not mix up with ramp up. IOW, mention exactly from where the value comes (e.g. Δt POWER UP TO AUDIO OUT TIMING table, depending on sampling clock rate). Otherwise you introduce quite loose property which will be including regulator ramp up in some cases...
Best regards, Krzysztof
Yes. This property is designed for power up to audio out timing. I need to clearly point this out.
Thank you very much for your suggestions!
Regards, Chancel Liu