Add the power controller node and the correspondending qos nodes for RK312x.
Signed-off-by: Alex Bee knaerzche@gmail.com --- arch/arm/boot/dts/rockchip/rk312x.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk312x.dtsi b/arch/arm/boot/dts/rockchip/rk312x.dtsi index 93560c4cd16a..617306a9edf7 100644 --- a/arch/arm/boot/dts/rockchip/rk312x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk312x.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/power/rk3128-power.h>
/ { compatible = "rockchip,rk3128"; @@ -133,6 +134,87 @@ smp-sram@0 { pmu: syscon@100a0000 { compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; reg = <0x100a0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3128-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3128_PD_VIO { + reg = <RK3128_PD_VIO>; + clocks = <&cru ACLK_RGA>, + <&cru ACLK_LCDC0>, + <&cru ACLK_IEP>, + <&cru ACLK_CIF>, + <&cru ACLK_VIO0>, + <&cru ACLK_VIO1>, + <&cru DCLK_VOP>, + <&cru DCLK_EBC>, + <&cru HCLK_RGA>, + <&cru HCLK_VIO>, + <&cru HCLK_EBC>, + <&cru HCLK_LCDC0>, + <&cru HCLK_IEP>, + <&cru HCLK_CIF>, + <&cru HCLK_VIO_H2P>, + <&cru PCLK_MIPI>, + <&cru SCLK_VOP>; + pm_qos = <&qos_rga>, + <&qos_iep>, + <&qos_lcdc>, + <&qos_vip>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_VIDEO { + reg = <RK3128_PD_VIDEO>; + clocks = <&cru ACLK_VEPU>, + <&cru ACLK_VDPU>, + <&cru HCLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru SCLK_HEVC_CORE>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3128_PD_GPU { + reg = <RK3128_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; + }; + + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_rga: qos@1012f000 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_iep: qos@1012f100 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc: qos@1012f180 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_vip: qos@1012f200 { + compatible = "rockchip,rk3128-qos", "syscon"; + reg = <0x1012f200 0x20>; };
gic: interrupt-controller@10139000 {