Hi Krzysztof,
On Fri, 17 Feb 2023 10:14:48 +0100 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org wrote:
On 16/02/2023 14:42, Herve Codina wrote:
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC such as MPC885 or MPC866.
Signed-off-by: Herve Codina herve.codina@bootlin.com
.../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 234 ++++++++++++++++++ include/dt-bindings/soc/fsl,tsa.h | 13 + 2 files changed, 247 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml create mode 100644 include/dt-bindings/soc/fsl,tsa.h
[...]
+patternProperties:
- '^tdm@[0-1]$':
- description:
The TDM managed by this controller- type: object
- additionalProperties: false
- properties:
reg:minimum: 0maximum: 1description:The TDM number for this TDM, 0 for TDMa and 1 for TDMb
[...]
fsl,rx-frame-sync-delay-bits:enum: [0, 1, 2, 3]maxItems: 1
The property is an enum Why this maxItems value ?
If I add the maxItems value, I've got some dt_binding_check errors: /xxxx/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml: patternProperties:^tdm@[0-1]$:properties:fsl,rx-frame-sync-delay-bits: 'enum' should not be valid under {'enum': ['const', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'minimum', 'maximum', 'multipleOf', 'pattern']} hint: Scalar and array keywords cannot be mixed from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
default: 0description: |Receive frame sync delay in number of bits.Indicates the delay between the Rx sync and the first bit of the Rxframe. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.fsl,tx-frame-sync-delay-bits:enum: [0, 1, 2, 3]maxItems: 1
Same question here.
Thanks for the review,
Hervé