On Mon, Jun 26, 2023 at 10:35:01AM +0800, Maso Huang wrote:
Add mt7986 audio afe document.
Signed-off-by: Maso Huang maso.huang@mediatek.com
.../bindings/sound/mediatek,mt7986-afe.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml
diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml new file mode 100644 index 000000000000..257327a33ea1 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt7986-afe.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt7986-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: MediaTek AFE PCM controller for MT7986
+maintainers:
- Maso Huang maso.huang@mediatek.com
+properties:
- compatible:
- oneOf:
- const: mediatek,mt7986-afe- items:- enum:- mediatek,mt7981-afe- mediatek,mt7988-afe- const: mediatek,mt7986-afe- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- clocks:
- minItems: 5
- items:
- description: audio bus clock- description: audio 26M clock- description: audio intbus clock- description: audio hopping clock- description: audio pll clock- description: mux for pcm_mck- description: audio i2s/pcm mck- clock-names:
- minItems: 5
- items:
- const: aud_bus_ck- const: aud_26m_ck- const: aud_l_ck- const: aud_aud_ck- const: aud_eg2_ck- const: aud_sel- const: aud_i2s_m
'aud_' is redundant.
+required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- assigned-clocks
- assigned-clock-parents
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/clock/mt7986-clk.h>
- afe@11210000 {
compatible = "mediatek,mt7986-afe";reg = <0x11210000 0x9000>;interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,<&infracfg_ao CLK_INFRA_AUD_26M_CK>,<&infracfg_ao CLK_INFRA_AUD_L_CK>,<&infracfg_ao CLK_INFRA_AUD_AUD_CK>,<&infracfg_ao CLK_INFRA_AUD_EG2_CK>;clock-names = "aud_bus_ck","aud_26m_ck","aud_l_ck","aud_aud_ck","aud_eg2_ck";assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,<&topckgen CLK_TOP_AUD_L_SEL>,<&topckgen CLK_TOP_A_TUNER_SEL>;assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,<&apmixedsys CLK_APMIXED_APLL2>,<&topckgen CLK_TOP_APLL2_D4>;- };
+...
2.18.0