Some of the signals are multiplexed, multiplexer configured at a signal request.
Signed-off-by: Piotr Wojtaszczyk piotr.wojtaszczyk@timesys.com --- Changes for v3: - Split previous commit for separate subsystems - Add pl08x virtual dma channels for i2s1 - Add dma mux handling, required when requesting tx dma signal for i2s1
arch/arm/mach-lpc32xx/phy3250.c | 111 +++++++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 5371bfaed799..2ec0411964f9 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c @@ -9,14 +9,18 @@ */
#include <linux/amba/pl08x.h> +#include <linux/amba/pl022.h> #include <linux/mtd/lpc32xx_mlc.h> #include <linux/mtd/lpc32xx_slc.h> #include <linux/of_platform.h> +#include <linux/spinlock.h>
#include <asm/mach/arch.h> #include "common.h" #include "lpc32xx.h"
+static DEFINE_SPINLOCK(lpc32xx_pl08x_lock); + static struct pl08x_channel_data pl08x_slave_channels[] = { { .bus_id = "nand-slc", @@ -30,11 +34,97 @@ static struct pl08x_channel_data pl08x_slave_channels[] = { .max_signal = 12, .periph_buses = PL08X_AHB1, }, + { + .bus_id = "i2s0-tx", + .min_signal = 13, + .max_signal = 13, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "i2s0-rx", + .min_signal = 0, + .max_signal = 0, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "i2s1-tx", + .min_signal = 10, + .max_signal = 10, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "i2s1-rx", + .min_signal = 2, + .max_signal = 2, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "ssp0-tx", + .min_signal = 15, + .max_signal = 15, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "ssp0-rx", + .min_signal = 14, + .max_signal = 14, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "ssp1-tx", + .min_signal = 11, + .max_signal = 11, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, + { + .bus_id = "ssp1-rx", + .min_signal = 3, + .max_signal = 3, + .muxval = 1, + .periph_buses = PL08X_AHB1, + }, +}; + +struct lpc32xx_pl08x_mux { + int signal; + void __iomem *addr; + int bit; +}; + +/* From LPC32x0 User manual "3.2.1 DMA request signals" */ +static const struct lpc32xx_pl08x_mux dma_mux[] = { + {3, LPC32XX_CLKPWR_SSP_CLK_CTRL, 5}, + {10, LPC32XX_CLKPWR_I2S_CLK_CTRL, 4}, + {11, LPC32XX_CLKPWR_SSP_CLK_CTRL, 4}, + {14, LPC32XX_CLKPWR_SSP_CLK_CTRL, 3}, + {15, LPC32XX_CLKPWR_SSP_CLK_CTRL, 2}, };
static int pl08x_get_signal(const struct pl08x_channel_data *cd) { - return cd->min_signal; + const int signal = cd->min_signal; + unsigned long flags; + int i, tmp; + + /* Set corresponding dma mux bit if muxed */ + for (i = 0; i < ARRAY_SIZE(dma_mux); i++) { + if (dma_mux[i].signal == signal) { + spin_lock_irqsave(&lpc32xx_pl08x_lock, flags); + tmp = __raw_readl(dma_mux[i].addr); + if (cd->muxval) + tmp |= BIT(dma_mux[i].bit); + else + tmp &= ~BIT(dma_mux[i].bit); + __raw_writel(tmp, dma_mux[i].addr); + spin_unlock_irqrestore(&lpc32xx_pl08x_lock, flags); + break; + } + } + return signal; }
static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) @@ -61,12 +151,31 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = { .dma_filter = pl08x_filter_id, };
+static struct pl022_ssp_controller lpc32xx_ssp_data[] = { + { + .bus_id = 0, + .enable_dma = 0, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp0-tx", + .dma_rx_param = "ssp0-rx", + }, + { + .bus_id = 1, + .enable_dma = 0, + .dma_filter = pl08x_filter_id, + .dma_tx_param = "ssp1-tx", + .dma_rx_param = "ssp1-rx", + } +}; + static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash", &lpc32xx_slc_data), OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash", &lpc32xx_mlc_data), + OF_DEV_AUXDATA("arm,pl022", 0x20084000, NULL, &lpc32xx_ssp_data[0]), + OF_DEV_AUXDATA("arm,pl022", 0x2008c000, NULL, &lpc32xx_ssp_data[1]), { } };